Senior Design 1987-88

Auto Dialer

By: Mike Norby, Dan Kanz, and Jeff Rooney
Advisor: Dr. B. W. Ellis

The telephone dialer will appear to be a standard telephone dial system. The actual phone numbers will be stored in a computer memory for ease of recall and automatic dialing. To dial, the user will pick up the receiver and select a letter corresponding to the last name of the person to be called; the door will open to display all the names with that letter and at the same time the internal computer will record the letter that was pushed. After the door is opened, the user will select from the list of names displayed by pushing the corresponding button. The telephone number will be automatically dialed.

Digital Controller

By: Jeff Bagstad
Advisor: Dr. A. Narayana

The purpose of this project was to implement a digital controller using a PC. The controller consists of two parts, hardware and software. The hardware component consisted of a printed circuit board containing the necessary hardware for the controller. The software component consisted of Turbo Basic programs and assembly language programs.

Digital Control of a Three-Phase Induction Motor

By: Dale Gill, Mike Hanson, and Mike Saunders
Advisor: Dr. Aswartha Narayana

Our project was to design and construct a motor speed control unit. The design uses pulse width modulation and a phase controlled rectifier. These two functions will control the amplitude and frequency of the motor supply voltage and, therefore, the motor speed.

Ethernet Project

By: Luke Friendshuh, Randall Schmidt, and Jim Anklan
Advisor: Dr. K. J. Miller

This project was an exercise in inter-computer communications. It consisted of three main parts: STARLAN SYSTEM- an exercise in communication with "Ethernet Style" data packet, CHEAPERNET SYSTEM- the complete hardware design and basic software development of a Cheapernet Local Area Network Exercise System, TRANSPUTER SYSTEM- exercises in communicating with INMOS Transputer chips.

HyperCube Project

By: Robert Penas and Gordon Anderson
Advisor: Dr. K. J. Miller

This project was to construct the control board (8086/8087) design. The PC prototype board for communication with the hypercube also was designed and constructed.

HyperCube Project Documentation

By: Jim Reinert and Brian Holthaus
Advisor: Dr. K. Miller

This paper outlines the design and construction of a microprocessor based hypercube parallel processing computer being designed and constructed at
St. Cloud State University. The prototype system, designed primarily for scientific applications, will be expandable to 16 nodes each based on the Intel 80186/8087 processor and numeric co-processor combination. The system host will be an IBM-PC computer. The long-term goal of this project is to produce a high performance computer using off the shelf technology costing only a fraction of the amount paid for conventional supercomputers. At the present time, hardware and preliminary communications software are nearly complete with plans to have an operational four-node system by late spring 1987.

Image Display Processing Package (see also 1988-89)

By: Karen Christenson
Advisor: Dr. Yi Zheng

The purpose of this project was to develop a display package for image processing applications on the SUN workstation. The package was developed with the use of SunView structure and functions, the Pixrect graphics library structures and functions, and C language.

Integrated Circuit Chip Tester

By: Benjamin Buxton, Michael Radovich, and Robert Zaun
Advisor: Dr. S. Lekhakul

Our group designed and constructed a device capable of testing integrated circuit logic chips. This device is capable of testing virtually all fourteen and sixteen pin digital chips in the lab with some limitations. Our device cannot test analog chips that require different voltage levels, high impedance states, or chips that are drawing high current.

Microprocessor Controlled Synthesizer

By: Tammy Goetz, Jared Larson, and Jeff Thon
Advisor: Dr. B. W. Ellis

The project objective was to design and build a microprocessor-based polyphonic musical synthesizer. This synthesizer was to be capable of generating tones according to events on a standard organ style keyboard. It was also to provide control over sound parameters such as amplitude envelope, harmonic content, and overall volume while monitoring the keyboard or reading from prepared music files.

Packet-Radio Project

By: Richard L. Meyers, James W. Rosenow, and E. Todd Volkmeier
Advisor: Dr. B. W. Ellis

The objective for this project was to build a packet-radio system (minus the radios) on an IBM PC expansion card and to develop the accompanying software. This system would implement the AX.25 Link Layer protocol.

PC Controller

By: Sherry Lauck and Martin Miller
Advisor: Dr. A. Narayana

The project was to design a PC controller consisting of a hardware and software implementation of a first and second order digital filter. The hardware consisted of three major areas of concern: analog/digital conversion, digital/analog conversion, and chip selection. The software consists of a monitor routine written in Turbo Basic and a filter routine written in assembly.

Sampling 8096 Micro Controller Project

By: Mike A. King
Advisor: Dr. K. J. Miller

With the 8096 micro-controller's internal analog to digital conversion capabilities, the project intent was to sample external analog signals and store their corresponding digital representation in the on-board 8096 RAM. These digital values would be held in a RAM array and held there for further conversion to Fourier Transform data by the internal math capabilities of the 8096. As time would have it, I was unable to go this far in the project and was only able to output the sampled data from the Ram array to an external 10 bit Digital to Analog Converter. The digital data was outputted through the appropriate 8096 ports to the D/A. All the data sampling and outputting was done on a timed basis and was implemented with the 8096's internal timers. The analog data outputted from the D/A was viewed on an oscilloscope and was noted as being extremely accurate in comparison to the input analog wave in the 8096.

SDLC Communication With the Intel Multi-Protocol Serial Controller

By: Charles Martin Bergquist

This paper described a synchronous, half-duplex, SDLC communications channel. The channel was operated in the Intel 80186 environment. The physical connection between nodes was the IEEE 485 standard communication link. Data transfers could be accomplished through either polled or DMA modes. The main component of the hardware is Intel's 8274 Multi-Protocol Serial Controller. Timing characteristics for the device were described. Programming explanations for both the polled and DMA modes were also included. The final sections were devoted to use of equipment and procedures for development and testing purposes.

Senior Design Project

By: Bill Krogfoss
Advisor: Dr. A. Narayana

During the 1987-1988 school year, I worked at a communications firm in Chatsworth, California. My senior design project was to be the work I was involved in over the school year. Since my circumstances were different than for the normal matriculated student, my senior design project did not take on the same format as the other students. My work, and therefore my senior design project, was dictated by the needs of the company. A great deal of my work was in the development and design verification of LAN products, however there is other work that I will mention.

Single-Field Video Digitizer

By: Kevin Sauer and Randall Shay
Advisor: Dr. S. Lekhakul

The objective of our project was to develop a circuit to convert a video image into a digital array of picture elements (pixels). Each pixel would be represented by a binary value corresponding to the brightness of the image. This image is then transmitted to the VAX computer where it will be processed and displayed.

Software Development for Image Processing

By: Van Y. Phan
Advisor: Dr. Y. Zheng

The objective of this project was to develop the software for image enhancement, reconstruction, and feature abstraction. The software performed: one and two-dimensional convolution, one and two-dimensional deconvolution by Weiner filter, image edge detection by modified masking function, image enhancement by modified histogram equalization and Homomorphic filter, and simulation.

System Design Kit Based on the Intel 80186 Central Processor

By: Tom Welle, Jerome Meyer, and Mike Peterson
Advisor: Dr. S. Lekhakul

Design a kit similar to that of the SDK-86. The intent is to be able to load programs into memory, run them, and then be able to examine how and if the system registers have become modified to the expected values. Any desired output can be written to the display board in the users program.

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