Course
Syllabus (Spring 2003)
ECE 482/582 Design of Integrated Circuits
Instructor: Dr. Tim Vogt
Office, Telephone: ECC210, 255-2997
Email: tjvogt@stcloudstate.edu
Class hours and location: 2:00-2:50 pm, M,
W, F, ECC 126
Lab hours and location:
2:00-3:50 pm, F, ECC 127
Office hours:
M-Th, 4:00-5:00 pm
Prereq: EE 322, EE 381
Textbook: “Digital Integrated Circuits: A
Design Perspective”, Rabaey, Chandrasakan, and Nikolic
Course Description: Design, and fabrication of integrated circuits. Semiconductor processing and design rules. Circuit techniques for designing logic circuits, sense amplifiers, and clock circuits. Wafer probing, failure analysis, and yield improvement. Economic and technological trends. Design Project. (EE582 students will be required to complete an additional design project beyond the basic requirement for the EE482 students)
Course objective: Provide an introduction to the basics of integrated circuit technology and design, including IC device, fabrication, and design principles.
Outcomes: Students will learn the basic requirements needed for the design and fabrication of integrated circuits. Using their understanding of fundamental technology and circuit functions they will be able to take a design project from concept to fabrication. The students will also be introduced to one of the industry leading software tools for VLSI design and will use the tools for the design of a semester project covering all the basic aspects of introductory IC design.
Course contents and
schedule:
Topic
Schedule
Introduction to VLSI (Chapter1)
0.5 weeks
Manufacturing, layout, Design rules (Chapter 2)
1.5 weeks
MOS transistors (Chapter
3)
2 weeks
Interconnect characteristics (Chapter
4)
2 weeks
CMOS inverter (Chapter 5)
2 weeks
Combinational logic (Chapter 6) 1.5 weeks
Sequential Logic (Chapter 7) 1 week
Implementation methods, design tools (chapter 8) 1 week
Synthesis (Insert F) 0.5 weeks
Interconnect Effects (Chapter 9) 1 week
Memory and array structures 2 weeks
Assessment for
student performance and course teaching:
· Problem assignment: ~1 homework set/week
· Laboratory: 6 basic labs during semester (2hrs each)
· Design Project: NONE
· Tests: 2 midterms (2hrs each), 1 final
Grading Policy:
· Labs: 20% (open labs)
· Homework: 20%
· Design Project: 0%
· Midterm Examinations: 2x20% each = 40% total
· Final Exam: 20%
· No Late submissions for labs, homework, and project! Late=0%
Notes:
· Grade based on curve using above points.
· Midterms and final can only be rescheduled if an excused absence is obtained from the instructor in advance.
