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St. Cloud State University

St. Cloud State University

Digital Logic Design

Instructor:Dr.S.Lekhakul                                                                                                     

Office: ECC 206                         

Phone:  308-4920 (Office), 259-5682 (Home)

E-mail:  slekhakul@stcloudstate.edu

Classroom:   ECC 110                          Time:  MTW: 8:00-8:50 am

Lab: ECC 216    Time:  Lab Check-off on Tuesday: 8:00-10:00 am

 (Exclude the first two labs, you are expected to work and finish your labs before the lab check-off time!)

Office Hours:      12:00-4:00 pm, MTW

Prerequisite:       PHYS 234

Textbook:           Digital Logic and Microprocessor Design with VHDL, Enoch O. Hwang, ISBN 0-534-46593-5

Course Description:

Number systems, Boolean algebra, logic gates, combinational and sequential circuits.  MSI based design, programmable logic and memory devices.  VHDL synthesis, Computer aided analysis and simulation.  Lab with design emphasis.

Objective:

The objective of this course is to teach students for a good understanding of basic concepts and have a firm grasp of computer aided design (CAD) tools.  The main goals of this course are (1) to teach students the fundamental concepts in classical manual digital design and (2) to show clearly the way in which digital circuits are designed today, using VHDL and CAD tools.

Outcomes:

Upon completion of this course, students will understand both basic principles of digital system design using VHDL and the use of CAD tools in the design process.  Students will be able to easily enter a design in schematic capture and in VHDL into the state-of-the-art CAD system, compile the design into a selected device, simulate the functionality and detailed timing of the resulting circuit, and implement the designs in actual devices.

Assessment for student performance and course teaching:

  • There will be several homework to be assigned in regular basis.  All assigned homework will be collected and graded.
  • There will be several labs that will be assigned and turned in.  A late lab will be accepted but 5 points (out of 25 points) will be deducted for each late day.
  • There will be two course exams and a final exam (not comprehensive).
  • The final exam will be held on Thursday, 13 December 2007, from 8:00-10:00 am at room ECC 110.
  • Make up exam is allowed only on the emergency cases.  The make up exam will be given on the week of the final exam (December 14 – December 19) or by the instructor’s approval date and time.

Grading Policy

The relative values of the components of your final grade are as follows:

Homework        6%                             90 - 100%       A, A+

Labs                16%                             80 - 90%         B, B+, A-

Test #1            26%                             70 - 80%         C, C+, B-

Test #2            26%                             60 – 70%        D, D+, C-

Final Exam         26%                             below 60%    F

Attendance Policy

   

Academic dishonesty

Attendance is required for this class.  Students who miss more than 8 class meetings, the semester grade will be dropped by one letter grade.  Students who miss more than 12 class meetings will not be allowed to take the final exam.

*Academic dishonesty, including but not limited to, cheating, plagiarism, misrepresentation of student status, and resume falsification. Plagiarism includes, but is not limited to, the use by paraphrase or direct quotation, the published or unpublished work of another person without full and clear acknowledgment; unacknowledged use of materials prepared by another person or agency engaged in selling or otherwise providing term papers or other academic materials; and commercialization sale or distribution of class notes without the instructors' permission.

Student Handbook - http://www.stcloudstate.edu/studenthandbook/code/conduct.asp

Student(s) who violate the academic dishonesty described above will receive an F grade from this class.

Laboratory Report for ECE 221

The lab reports are required for all students.  Each laboratory experiment is worth 25 points, 15 points for lab check-off and 10 points for lab report.  Late lab will be accepted but 5 points will be deducted for each late day.  The lab report is due on Monday in the class room at 8:00 am.  If you are not attending the class on Monday, it will consider as a late.

The lab report must be typed using word processor.  The contents of the lab report are divided in paragraph as follows:

  • State the purpose of the experiment in a short paragraph (three or four lines).  Do not repeat the objective of the lab that given in the lab’s handout.
  • a)  Describe briefly each part of the lab.
    • Describe any difficulties or problems you have with the experiment.
    • Include a circuit diagram or a block diagram if needed.
    • Include a flowchart if needed.
    • Include a VHDL source code if needed.
    • Include a functional simulation waveform if needed.  Explanation is needed in the simulation waveform.

All circuit diagrams, flowcharts, VHDL codes, or functional simulation waveforms must be added in separate pages.

  • Answer all questions asked in the lab handout.

Length of the lab report is about one page (30-40 lines) writing (excluding figures, truth tables, or VHDL source codes), single spaces, all the margins are 1”, 12 pt. font.